1. Field of the Invention
The present invention relates generally to integrated circuit devices, and more specifically to input and output circuitry useful in a programmable logic device.
2. Description of the Prior Art
Programmable logic devices are becoming increasingly popular in the electronics industry because of their flexibility. These devices allow a user to configure a standard part to perform a wide variety of logic functions. Since a single standard device can be configured many different ways, the total cost of using such a device in a system can be significantly less than the cost of custom designed parts; especially in cases where product volume is not extremely large.
One popular type of programmable logic device has evolved from simpler programmable logic arrays (PLA). These devices include an AND-OR array. In such an array, a plurality of row input lines cross a plurality of product term output lines in such a manner that any row line may be connected to any or all of the product term lines. This is generally implemented as a rectangular grid of horizontal and vertical overlapping signal lines, with the capability of making a connection between two signal lines at each cross-point. The row lines all run in one direction, while the product term signal lines run at right angles to the row lines.
In general, row signal lines are provided to represent the true and inverted values for all input signals to the device. The connection of row signal lines to the product term signal lines provides the AND function of the array. Groups of product term signal lines are OR'd together to provide the OR function of the array. Each group of product term signal lines which are
OR'd together are connected to an output logic block which provides output signals to an input/output pin. These output logic blocks are often referred to as output logic macrocells (OLMC).
A typical programmable logic device has several dedicated input pins, which are used solely to provide input signals to the array. Input/output pins connected to the output logic macrocells can typically be programmed to function as output pins, being driven by the associated output logic macrocells, or as additional input pins. When an input/output pin is programmed to function as an input, the associated output logic macrocell is not used. Output logic macrocells typically include both combinatorial and sequential logic, either of which can be used to drive the input/output pin when it is programmed to provide an output signal. The functions of the output logic macrocells are defined at device program time as known in the art.
Many programmable logic devices also include multi-function input pins. These pins can be used as data inputs, in which case they function the same as the dedicated input pins. Alternatively, they can be programmed to perform various control functions, and are used to provide signals such as a device clock signal (used to drive sequential circuitry), input latch enable, and output enable. As is the case with the remainder of the device, these multi-function input pins are programmed to perform a selected function at device program time, with the programming information typically being stored in EEPROM or a similar non-volatile storage.
Additional inputs to the AND-OR array can be provided by feedback signals from the output logic macrocells. When the output logic macrocells are programmed to function in this manner, an output signal is generated which is applied to a row of the array. This feedback output signal may or may not be applied to the associated input/output pin. Such a programmed function for the output logic macrocell is often referred to as a buried logic function.
Physical limitations exist on the number of rows which can be provided in the array. A single row driver, which provides a true and inverted signal to the array, is typically connected to each output logic macrocell. If the cell is programmed to provide a buried output signal, such output signal is provided to this row driver. If the associated input/output pin is programmed to function as an input, it is connected to the same row driver, and the output logic macrocell is unused.
In programmable logic devices, it is always desirable, but often difficult, to make full use of the input and output pins of the device. Providing buried outputs and using input pins to provide control signals limits the number of pins which are available for use as input and output. Using input/output pins for input is also wasteful of resources, since the associated output logic macrocells are not used. It would be desirable to provide circuitry and a device design which allows as complete as possible use of all input and input/output pins on a device.